1. Field of the Invention
The present invention is related to a delta-sigma modulator, and a delta-sigma digital to analog converter (hereinafter, the digital to analog converter is referred to a DA converter) apparatus including the same delta-sigma modulator for changing an order of filter. In particular, the present invention is related to a delta-sigma DA converter apparatus used in a wireless receiver as required for use in, for example, a high-rate clock operation and to have a high SNR (Signal to Noise Ratio).
2. Description of the Related Art
Conversion of an analog signal into a digital signal enables a signal to be transmitted and processed easily and efficiently. Therefore, an analog-to-digital converter (referred to as an AD converter hereinafter) is an important function for a wireless receiver employed in a portable telephone or the like. According to acceleration of data rate to follow recent use of a broadband communication method, it is necessary even for an AD converter to simultaneously realize low power consumption, high-rate clock operation, and a high SNR. Accordingly, an operation clock of a delta-sigma AD converter that can easily realize a high SNR and that has been used in a measuring device or the like has been accelerated.
FIG. 17 is a block diagram showing a configuration of a variable-order delta-sigma modulator according to a first prior art disclosed in, for example, Japanese patent laid-open publication No. JP-2004-080152-A. Referring to FIG. 17, the variable-order delta-sigma modulator is configured to include integrators 71 to 73 each including a plurality of operational amplifiers, one-sample delay units 101 to 103 and 111 to 113, operational amplifiers 81 to 83 and 91 to 93, subtractors 121 to 125, a feedback circuit F11 including switches 61 and 62, a feedback circuit F12, a quantizer 65, a DA converter (DAC) 66, and a controller 60 controlling the switches 61 and 62 to be turned on or off. This variable-order digital-sigma modulator has a closed loop structure in which a digital output signal from the quantizer 65 is converted into an analog signal by the DA converter 66, and the analog signal is supplied to the subtractors 121, 122, and 124 via the feedback circuit F12. In this case, the variable-order digital-sigma modulator is configured to provide the switches 61 and 62 in the feedback circuit F12 to switch the order of a filter so as to deal with a plurality of systems. The filter of the modulator serves as a third-order filter when both the switches 61 and 62 are turned off, and serves as a second-order filter when only the switch 62 is turned on.
FIG. 18 is a block diagram showing a configuration of each of the integrators 71, 72, and 73 shown in FIG. 17. In FIG. 18, as well known, each of the integrators 71, 72, and 73 is a temporal integrator configured to include a subtractor 131 and a one-sample delay unit 132.
FIG. 19 is a block diagram showing a configuration of a variable-order delta-sigma modulator according to a second prior art disclosed in, for example, the Japanese patent laid-open publication No. JP-2004-080152-A. Referring to FIG. 19, the variable-order delta-sigma modulator is configured to include a plurality of integrators 71 to 75, one-sample delay units 101 to 105 and 111 to 114, operational amplifiers 81 to 85 and 91 to 94, subtractors 121 to 128, a feedback circuit F11 including switches 61 to 64, a feedback circuit F12, a quantizer 65, a DA converter (DAC) 66, and a controller 60a controlling the switches 61 to 64 to be turned on or off. A filter of the modulator shown in FIG. 19 serves as a maximum fifth-order filter when the switches 61 to 65 are all turned on.
According to the first and second prior arts, a signal band is a wide-band. However, the operational amplifier having the higher-order filter characteristic has such problems that the number of operational amplifiers increases to increase power consumption and a circuit area considerably increases. In order to solve the problems, a multiplexed-operational-amplifier circuit is proposed as a method of decreasing the number of operational amplifiers, in Jinseok Koh et al., “A 66 dB DR 1.2V 1.2 mW Single-Amplifier Double-Sampling 2nd-order ΔΣ ADC for WCDMA in 90 nm CMOS”, Solid-State Circuits Conference (SSCC) 2005, Digest of technical papers, Session 9, 9.3, pp. 170-171, Vol. 1, Feb. 6-10, 2005 (referred to as Jinseok Koh et al. hereinafter).
FIG. 20 is a block diagram showing a configuration of a delta-sigma modulator according to a third prior art disclosed in, for example, Jinseok Koh et al. Referring to FIG. 20, the delta-sigma modulator is configured as follows, as compared with the first and second prior arts. A feedback circuit F11 is configured to in parallel connect a feedback circuit constituted by an operational amplifier 91 to a feedback circuit constituted by an operational amplifier 142 and a one-sample delay unit 152. A feedback circuit F12 is configured to in parallel connect a feedback circuit constituted by an operational amplifier 91 to a feedback circuit constituted by an operational amplifier 92 and a one-sample delay unit 112. Namely, the delta-sigma modulator is configured to multiplex the integrator constituted by the operational amplifier in each of the feedback circuits F11 and F12.
The delta-sigma modulator shown in FIG. 20 is configured so that the feedback circuit F11 includes “n” output signals from the integrators (where “n” is a natural number equal to or larger than two) for “n” samplings (“n” delays) before to the sampling to be processed, and the feedback circuit F12 includes “n” output signals from the DA converters for “n” samplings (“n” delays) before to the sampling to be processed. The feedback signals from the respective feedback circuits F11 and F12 are fed back to a subtractor 121 connected to an input terminal of the integrator 71. It is thereby possible to exhibit an equivalent low-pass filter characteristic to that when “n” integrators are used, and to realize a higher SNR by an “n”-th-order noise shaping effect.
It is necessary for the delta-sigma modulator configured as stated above according to the third prior art to increase an integral capacity so as to realize a high SNR in a signal band having a narrow signal bandwidth and to reduce noise of the operational amplifier 81 of the first stage. In this case, kT/C noise is generated when the integral capacity samples thermal noise. When the integral capacity is Ch and a feedback capacity is Cs, then it is disadvantageously necessary to increase the feedback capacity Cs because of a constant gain ratio (Cs/Ch), and it is disadvantageously impossible to reduce current consumption.